In semiconductor device manufacturing, photolithography is one of the most important processes for integrated circuits (ICs). With the developments in semiconductor device manufacturing technology, the feature size continues to shrink, which requires higher resolution in photolithography. Photolithography resolution refers to the minimum feature size (also called the critical dimension, CD) that a photolithography tool can expose onto a wafer, which is an important performance indicator in photolithography technology.
In order to achieve smaller CD, resolution enhancement technologies have been used to expose a finer image on the photoresist and manufacture a semiconductor device near the photolithography resolution limits in mask making. The resolution enhancement technologies include the use of light sources with shorter wavelengths, and the use of phase-shift masks and off-axis illumination (OAI). OAI is currently the most common resolution enhancement technology, which can improve the traditional resolution by 50 percent and increase the depth of focus (DOF). However, OAI may cause the optical proximity effect (OPE).
In order to reduce the OPE, the pattern on the mask undergoes Optical Proximity Correction (OPC). However, when used for hole patterns, conventional OPC methods may have modified patterns formed on the mask with an EPE (i.e., edge placement error) exceeding a predetermined range due to mask rule restrictions.
Therefore, there is a need to solve these and other problems and to provide a method for correcting layout pattern and a mask thereof.